1. Field of the Invention
The invention relates to a phase locked loop, and in particular to a phase locked loop utilizing frequency folding.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional digital phase locked loop (DPLL) 100. As shown, the conventional phase locked loop 100 comprises a phase-frequency detector (PFD) 110, a controller 120, a digitally controlled oscillator (DCO) 130 comprising a fine tune circuit (FTC) 132 and a coarse tune circuit (CTC) 134, and a loop divider 140. The PFD 110 receives and detects the phase and frequency difference between a reference clock signal SR and a feedback clock signal SF, and generates a phase detection clock signal SPD based on whether the feedback clock signal SF is leading or lagging the reference clock signal SR. The phase detection clock signal SPD comprises an up control signal SU and a down control signal SD respectively determining whether the DCO 130 needs to generate an output clock signal SO with a higher or lower frequency (i.e. lower or higher period). The PFD 110 then provides the phase detection clock signal SPD to the controller 120.
The controller 120 generates a control word CW comprising a first control word CW1 and a second control word CW2 according to the phase detection clock signal SPD and then provides the first and second control words CW1 and CW2 respectively to the FTC 132 and CTC 134 within the DCO 130 to control the period of the output clock signal SO generated by the DCO 130. The first and second control words CW1 and CW2 respectively determine a high-resolution part and a low-resolution part of the period of the output clock signal SO Typically, the first and second control words CW1 and CW2 respectively are thermal code and one-hot code, as is described in relation to FIG. 3.
FIG. 2 shows the period T of the output clock signal SO corresponding to the control word CW, illustrating the relationship of the high and low resolution parts of the output clock signal SO respectively with the first and second control word CW1 and CW2 of the control word CW. As shown, the period range TWHOLE of the output clock signal SO is separated into a plurality of partially overlapped sub-period ranges T1, T2 and so on to TM respectively corresponding to the second control word CW2=CW2 (1), CW2(2) and so on to CW2 (M). Each of the sub-period ranges T1 to TM is further separated into a plurality of sub-period ranges T11-TN1, T12-TN2, and so on to T1M-TNM. The sub-period ranges T11, T12, and so on to T1M all correspond to the first control word CW1=CW1 (1). Similarly, the sub-period ranges T21, T22, and so on to T2M all correspond to the first control word CW1=CW1 (2). The other sub-period ranges can also be analogized. The sub-period ranges T1 to TM with larger intervals belong to the low resolution part of the output clock signal SO, and the sub-period ranges T11 to TN1, T12 to TN2, and so on to T1M to TNM with smaller intervals belonging to the high resolution part of the output clock signal SO.
When the FTC 132 and CTC 134 respectively receive the first and second control word CW1 and CW2, they cooperate to generate the output clock signal SO with a period having high and low resolution parts respectively corresponding to the first and control words CW1 and CW2, and then provides the output clock signal SO to the loop divider 140. Note that in the figure, the output clock signal SO generated by the CTC 134 and a fine-tune output clock signal SFO generated by the FTC 132 have the same frequency but different phases, thus, the fine-tune output clock signal SFO can replace the output clock signal SO to serve as an output of the DCO 130 to be provided to the loop divider 140.
The loop divider 140 divides the frequency of the output clock signal SO by a predetermined integer to generate the feedback clock signal SF. As is well-known to those skilled in the art, the loop divider 140 can be removed such that the output clock signal SO is connected directly to the phase-frequency detector 110 to serve as the feedback clock signal SF.
FIG. 3 is a schematic diagram of the DCO 130 in FIG. 1. As shown, the FTC 132 comprises delay buffers 31_1 to 31_N, and the CTC 134 comprises first delay buffers 32_1 to 32_M and second delay buffers 33_1 to 33_M. The delay buffers 31_1 to 31_N of the FTC 132 are respectively turned on or off according to one bit of the first control word CW1 (an N-bit thermal code) to provide different driving power to the CTC 134. Similarly, the first delay buffers 32_1 to 32_M of the CTC 134 are respectively turned on or off according to one bit of the second control words CW2 (a M-bit one-hot code) to provide different delay paths to fine-tune output clock signal SFO from the FTC 132. As a result the FTC 132 and CTC 134 cooperate to generate the output clock signal SO with a period having high and low resolution parts respectively corresponding to the first and second control words CW1 and CW2.
The conventional DPLL 100, however, has several disadvantages. First, the CTC 134 occupies a large area of a chip for providing a sufficiently long delay period and hence broad bandwidth of the output clock signal SO. Second, the controller 120 has high hardware complexity and requires a large chip area to generate the second control code CW2 in one-hot code form. Third, as shown in FIG. 4, the period T of the output clock signal SO corresponding to control word CW in an unwanted case results from fabrication process variation, where the two adjacent first sub-period ranges T2 and T3 are not overlapped, inducing a forbidden period range TF and hence jitter of the output clock signal SO. To prevent this, a complicated design procedure and lengthy simulation are required to ensure that all of the first sub-period ranges T1-TM are partially overlapped.